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HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Switching Regulator for Chopper Type DC/DC Converter
REJ03F0055-0200Z (Previous: ADE-204-020A) Rev.2.0 Sep.18.2003
Description
The HA16114P/FP/FPJ and HA16120FP/FPJ are single-channel PWM switching regulator controller ICs suitable for chopper-type DC/DC converters. Integrated totem-pole output circuits enable these ICs to drive the gate of a power MOSFET directly. The output logic of the HA16120 is designed to control a DC/DC step-up (boost) converter using an N-channel power MOS FET. The output logic of the HA16114 is designed to control a DC/DC step-down (buck) converter or inverting converter using a P-channel power MOS FET. These ICs can operate synchronously with external pulse, a feature that makes them ideal for power supplies that use a primary-control AC/DC converter to convert commercial AC power to DC, then use one or more DC/DC converters on the secondary side to obtain multiple DC outputs. Synchronization is with the falling edge of the `sync' pulse, which can be the secondary output pulse from a flyback transformer. Synchronization eliminates the beat interference that can arise from different operating frequencies of the AC/DC and DC/DC converters, and reduces harmonic noise. Synchronization with an AC/DC converter using a forward transformer is also possible, by inverting the `sync' pulse. Overcurrent protection features include a pulse-by-pulse current limiter that can reduce the width of individual PWM pulses, and an intermittent operating mode controlled by an on-off timer. Unlike the conventional latched shutdown function, the intermittent operating function turns the IC on and off at controlled intervals when pulse-by-pulse current limiting continues for a programmable time. This results in sharp vertical settling characteristics. Output recovers automatically when the overcurrent condition subsides. Using these ICs, a compact, highly efficient DC/DC converter can be designed easily, with a reduced number of external components.
Functions
* 2.5 V voltage reference * Sawtooth oscillator (Triangle wave) * Overcurrent detection * External synchronous input * Totem-pole output * Undervoltage lockout (UVL) * Error amplifier * Vref overvoltage protection (OVP)
Rev.2.0, Sep.18.2003, page 1 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Features
* Wide supply voltage range: 3.9 V to 40 V* * Maximum operating frequency: 600 kHz * Able to drive a power MOS FET (1 A maximum peak current) by the built-in totem-pole gate predriver circuit * Can operate in synchronization with an external pulse signal, or with another controller IC * Pulse-by-pulse overcurrent limiting (OCL) * Intermittent operation under continuous overcurrent * Low quiescent current drain when shut off by grounding the ON/OFF pin HA16114: IOFF = 10 A (max) HA16120: IOFF = 150 A (max) * Externally trimmable reference voltage (Vref): 0.2 V * Externally adjustable undervoltage lockout points (with respect to VIN) * Stable oscillator frequency * Soft start and quick shut function Note: The reference voltage 2.5 V is under the condition of VIN 4.5 V.
Ordering Information
Hitachi Control ICs for Chopper-Type DC/DC Converters
Product Channels Dual Number HA17451 Channel No. Ch 1 Ch 2 Single HA16114 HA16120 Dual HA16116 -- -- Ch 1 Ch 2 HA16121 Ch 1 Ch 2 Control Functions Step-Up -- -- -- -- Step-Down -- -- Inverting -- -- -- Totem pole power MOS FET driver Pulse-by-pulse current limiter and intermittent operation by on/off timer Output Circuits Open collector Overcurrent Protection SCP with timer (latch)
Rev.2.0, Sep.18.2003, page 2 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Pin Arrangement
GND*1
1 2 3 4 5 6 7 8 (Top view)
16 15 14 13 12 11 10 9
Vref ADJ DB ON/OFF TM CL(-) VIN OUT
SYNC
RT CT IN(-) E/O IN(+) P.GND*1
Note: 1. Pin 1 (GND) and Pin 8 (P.GND) must be connected each other with external wire.
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND SYNC RT CT IN(-) E/O IN(+) P.GND OUT VIN CL(-) TM ON/OFF DB ADJ Vref Function Signal ground External sync signal input (synchronized with falling edge) Oscillator timing resistor connection (bias current control) Oscillator timing capacitor connection (sawtooth voltage output) Inverting input to error amplifier Error amplifier output Non-inverting input to error amplifier Power ground Output (pulse output to gate of power MOS FET) Power supply input Inverting input to current limiter Timer setting for intermittent shutdown when overcurrent is detected (sinks timer transistor current) IC on/off control (off below approximately 0.7 V) Dead-band duty cycle control input Reference voltage (Vref) adjustment input 2.5 V reference voltage output
Rev.2.0, Sep.18.2003, page 3 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Block Diagram
Vref 16 ADJ 15 DB 14 ON/OFF 13 TM 12 CL(-) 11 VIN 10 OUT 9
ADJ
VIN
ON/OFF from UVL UVL H L VL VH OVP Triangle waveform generator
1.6 V 1.0 V
1k 0.3V
-
0.2 V
+
CL Vref
2.5V bandgap reference voltage generator
UVL output
Latch
SQ R
PWM COMP
+ - +
from UVL OUT
VIN
*1 NAND (HA16114)
0.3 V Latch reset pulses 1.1 V RT Bias current 1 GND 2 3 RT 4 CT
1k from UVL
+ -
EA
5 IN(-)
6 E/O
7 IN(+)
8 P.GND
SYNC
Note: 1. The HA16120 has an AND gate.
Rev.2.0, Sep.18.2003, page 4 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Timing Waveforms
Generation of PWM pulse output from sawtooth wave (during steady-state operation) T= Dead-band voltage (at DB) 1.6 V typ 1 fOSC
Sawtooth wave (at CT) Error amplifier output (at E/O) 1.0 V typ
HA16114 PWM pulse output (drives gate of P-channel power MOS FET)
VIN
Off On
Off On
Off On
Off On
Off On
0V
HA16120 PWM pulse output (drives gate of N-channel power MOS FET)
VIN
On Off Off
On Off
On Off
On Off
On
0V tON T
Time t Note: On duty =
Rev.2.0, Sep.18.2003, page 5 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Guide to the Functional Description
The description covers the topics indicated below.
Oscillator 1. frequency (fOSC) control and synchronization
GND*1
1 2 3 4 5 6 7 8 (Top view)
16 15 14 13 12 11 10 9
Vref ADJ DB ON/OFF TM CL(-) VIN OUT
SYNC
RT CT IN(-)
Vref adjustment, undervoltage 5. lockout, and overcurrent protection
DC/DC output 2. voltage setting and error amplifier usage
6. ON/OFF pin usage
3.
Dead-band and soft-start settings
E/O IN(+)
Intermittent 7. mode timing during overcurrent
Output stage and 4. power MOS FET driving method
P.GND*1
8.
Setting of current limit
Note: 1. P.GND is a high-current (1 A maximum peak) ground pin connected to the totem-pole output circuit. GND is a low-current ground pin connected to the Vref voltage reference. Both pins must be grounded.
1. Sawtooth Oscillator (Triangle Wave) 1.1 Operation and Frequency Control The sawtooth wave is a voltage waveform from which the PWM pulses are created (See figure 1). The sawtooth oscillator operates as follows. A constant current IO determined by an external timing resistor RT is fed continuously to an external timing capacitor CT. When the CT pin voltage exceeds a comparator threshold voltage VTH, the comparator output opens a switching transistor, allowing a 3IO discharge current to flow from CT. When the CT pin voltage drops below a threshold voltage VTL, the comparator output closes the switching transistor, stopping the 3IO discharge. Repetition of these operations generates a sawtooth wave. The value of IO is 1.1 V/RT . The IO current mirror has a limited current capacity, so RT should be at least 5 k (IO 220 A). Internal resistances RA, RB, and RC set the peak and valley voltages VTH and VTL of the sawtooth waveform at approximately 1.6 V and 1.0 V.
Rev.2.0, Sep.18.2003, page 6 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ The oscillator frequency fOSC can be calculated as follows.
fOSC = Here, t1 = t2 = 1 t 1 + t2 + t3 CT x (VH - VL) 1.1 V/RT CT x (VH - VL) 3 x 1.1 V/RT
t3 0.8 s (comparator delay time) Since VH - VL = 0.6 V fOSC 1 (Hz) 0.73 x CT x RT + 0.8 (s)
At high frequencies the comparator delay causes the sawtooth wave to overshoot the 1.6 V threshold and undershoot the 1.0 V threshold, and changes the dead-band thresholds accordingly. Select constants by testing under implementation conditions.
3.2 V (Internal voltage) Current mirror CT charging IO Oscillator comparator 1.1 V 1:4 Discharg -ing 3IO RC RB Sync circuit RT CT IO External circuit VH = 1.6 V typ
Vref 2.5 V RA
SYNC
t2 t1
VL = 1.0 V typ
t1 : t 2 = 3 : 1
Figure 1.1 Equivalent Circuit of Oscillator
Rev.2.0, Sep.18.2003, page 7 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 1.2 External Synchronization These ICs have a sync input pin so that they can be synchronized to a primary-control AC/DC converter. Pulses from the secondary winding of the switching transformer should be dropped through a resistor voltage divider to the sync input pin. Synchronization takes place at the falling edge, which is optimal for multiple-output power supplies that synchronize with a flyback AC/DC converter. The sync input pin (SYNC) is connected internally through a synchronizing circuit to the sawtooth oscillator to synchronize the sawtooth waveform (see figure 1.2). * Synchronization is with the falling edge of the external sync signal. * The frequency of the external sync signal must be in the range fOSC < fSYNC < fOSC x 2. * The duty cycle of the external sync signal must be in the range 5% < t1/t2 < 50% (t1 = 300 ns Min). * With external synchronization, VTH' can be calculated as follows.
VTH' = (VTH - VTL) x fOSC + VTL fSYNC
Note: When not using external synchronization, connect the SYNC pin to the Vref pin.
VTH (1.6 V typ) Sawtooth wave (fOSC) VTL (1.0 V typ) VTH'
SYNC pin
(fSYNC) Synchronized at falling edge t1 t2 1V
Vref
Figure 1.2 External Synchronization
Rev.2.0, Sep.18.2003, page 8 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 2. DC/DC Output Voltage Setting and Error Amplifier Usage 2.1 DC/DC Output Voltage Setting 1. Positive Output Voltage (VO > Vref)
HA16114 with step-down topology VIN IN(-) IN(+)
- +
HA16120 with step-down (boost) topology VIN CL EA VO GND OUT
+ -
CL EA GND
+ -
OUT VO
IN(-) IN(+)
- +
Vref
Vref
R2
R1 VO = Vref x R1 + R2 R2
R2
R1
Figure 2.1 Output Voltage Setting (1) 2. Negative Output Voltage (VO < 0 V)
HA16114 with inverting topology VIN
- +
CL EA OUT
IN(-) IN(+)
Vref R3 R4
- +
R2 VO = -Vref x
R1 R3 R1 + R2 x -1 R2 R3 + R4
Figure 2.2 Output Voltage Setting (2)
Rev.2.0, Sep.18.2003, page 9 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 2.2 Error Amplifier Usage Figure 2.3 shows an equivalent circuit of the error amplifier. The error amplifier in these ICs is a simple NPN-transistor differential amplifier with a constant-current-driven output circuit. The amplifier combines a wide bandwidth (fT = 4 MHz) with a low open-loop gain (50 dB Typ), allowing stable feedback to be applied when the power supply is designed. Phase compensation is also easy.
IC internal VIN
IN(-) IN(+) 80 A 40 A
E/O To internal PWM comparator
Figure 2.3 Error Amplifier Equivalent Circuit 3. Dead-Band Duty Cycle and Soft-Start Settings 3.1 Dead-Band Duty Cycle Setting The dead-band duty cycle (the maximum duty cycle of the PWM pulse output) can be programmed by the voltage VDB at the DB pin. A convenient way to obtain VDB is to divide the IC's Vref output by two external resistors. The dead-band duty cycle (DB) and VDB can be calculated as follows.
VTH - VDB x 100 (%) This applies when VDB > VTL. VTH - VTL If VDB < VTL, there is no PWM output. R2 VDB = Vref x R1 + R2 DB =
Note: VDB is the voltage at the DB pin. VTH: 1.6 V (Typ) VTL: 1.0 V (Typ) Vref is typically 2.5 V. Select R1 and R2 so that 1.0 V VDB 1.6 V.
Sawtooth wave - DB E/O + + R2 from UVL Sawtooth wave PWM COMP VTH VDB VTL Dead band Note: VTH and VTL vary depending on the oscillator. Select constants by testing under implementation conditions. Voltage at DB pin
To Vref R1 VDB
Figure 3.1 Dead-Band Duty Cycle Setting
Rev.2.0, Sep.18.2003, page 10 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 3.2 Soft-Start Setting Soft-start avoids overshoot at power-up by widening the PWM output pulses gradually, so that the converted DC output rises slowly. Soft-start is programmed by connecting a capacitor between the DB pin and ground. The soft-start time is determined by the time constant of this capacitor and the resistors that set the voltage at the DB pin.
tsoft = -C1 x R x ln (1 - R= R1 x R 2 R1 + R2 R2 R1 + R 2 VX ) VDB
VDB = Vref x
Note: VX is the voltage at the DB pin after time t (VX < VDB).
Undervoltage lockout released Sawtooth To Vref wave - VX R1 DB + C1 R2 from UVL UVL sink transistor t Soft-start time tsoft E/O + PWM COMP VTH VDB VTL 1.0 V VX 1.6 V Sawtooth wave
Figure 3.2 Soft-Start Setting 3.3 Quick Shutdown The quick shutdown function resets the voltages at all pins when the IC is turned off, to assure that PWM pulse output stops quickly. Since the UVL pull-down resistor in the IC remains on even when the IC is turned off, the sawtooth wave output, error amplifier output, and DB pin are all reset to low voltage. This feature helps in particular to discharge capacitor C1 in figure 3.2, which has a comparatively large capacitance. In intermittent mode (explained on a separate page), this feature enables the IC to soft-start in each on-off cycle.
Rev.2.0, Sep.18.2003, page 11 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 4. PWM Output Circuit and Power MOSFET Driving Method These ICs have built-in totem-pole push-pull drive circuits that can drive a power MOS FET as shown in figure 4.1. The power MOS FET can be driven directly through a gate protection resistor. If VIN exceeds the gate breakdown voltage of the power MOS FET additional protective measures should be taken, e.g. by adding Zener diodes as shown in figure 4.2. To drive a bipolar power transistor, the base should be protected by voltage and current dividing resistors as shown in figure 4.3.
VIN To CL Bias circuit OUT RG Gate protection resistor Totem-pole output circuit P.GND
Example: P-channel power MOSFET VO
Figure 4.1 Connection of Output Stage to Power MOS FET
VIN RG OUT GND DZ VO
Example: N-channel power MOSFET
Figure 4.2 Gate Protection by Zener Diodes
VIN OUT GND
Base current limiting resistor
VO
Base discharging resistor Example: NPN power transistor
Figure 4.3 Driving a Bipolar Power Transistor
Rev.2.0, Sep.18.2003, page 12 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 5. Voltage Reference (Vref = 2.5 V) 5.1 Voltage Reference A bandgap reference built into the IC (see figure 5.1) outputs 2.5 V 50 mV. The sawtooth oscillator, PWM comparator, latch, and other internal circuits are powered by this 2.5 V and an internally-generated voltage of approximately 3.2 V. The voltage reference section shut downs when the IC is turned off at the ON/OFF pin as described later, saving current when the IC is not used and when it operates in intermittent mode during overcurrent.
VIN ON/OFF
- +
1.25 V Sub bandgap circuit 25 k 1.25 V 25 k Main bandgap circuit
3.2 V Vref 2.5 V ADJ
Figure 5.1 Vref Reference Circuit 5.2 Trimming the Reference Voltage (Vref and ADJ pins) Figure 5.2 shows a simplified circuit equivalent to figure 5.1. The ADJ pin in this circuit is provided for trimming the reference voltage (Vref). The output at the ADJ pin is a voltage VADJ of 1.25 V (Typ) generated by the bandgap circuit. Vref is determined by VADJ and the ratio of internal resistors R1 and R2 as follows:
Vref = VADJ x R1 + R 2 R2
The design values of R1 and R2 are 25 k with a tolerance of 25%. If trimming is not performed, the ADJ pin open can be left open.
VIN
Vref R1 ADJ R2
25 k (typ) 25 k (typ)
- + VBG (bandgap voltage) 1.25 V (typ)
Figure 5.2 Simplified Diagram of Voltage Reference Circuit
Rev.2.0, Sep.18.2003, page 13 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ The relation between Vref and the ADJ pin enables Vref to be trimmed by inserting one external resistor (R3) between the Vref and ADJ pins and another (R4) between the ADJ pin and ground, to change the resistance ratio. Vref is then determined by the combined resistance ratio of the internal R1 and R2 and external R3 and R4.
Vref = VADJ x RA + R B RB
Where, RA: parallel resistance of R1 and R3 RB: parallel resistance of R2 and R4 Although Vref can be trimmed by R3 or R4 alone, to decrease the temperature dependence of Vref it is better to use two resistors having identical temperature coefficients. Vref can be trimmed in the range of 2.5 V 0.2 V. Outside this range, the bandgap circuit will not operate and the IC may shut down.
Vref R3 R4 ADJ R1 R2 RA = Internal resistors RB = R1 R3 R1 + R 3 R2 R4 R2 + R 4
External resistors
Figure 5.3 Trimming of Reference Voltage 5.3 Vref Undervoltage Lockout and Overvoltage Protection The undervoltage lockout (UVL) function turns off PWM pulse output when the input voltage (VIN) is low. In these ICs, this is done by monitoring the Vref voltage, which normally stays constant at approximately 2.5 V. The UVL circuit operates with hysteresis: it shuts PWM output off when Vref falls below 1.7 V, and turns PWM output back on when Vref rises above 2.0 V. Undervoltage lockout also provides protection in the event that Vref is shorted to ground. The overvoltage protection circuit shuts PWM output off when Vref goes above 6.8 V. This provides protection in case the Vref pin is shorted to VIN or another high-voltage source.
PWM output PWM output off PWM output on PWM output off
1.7 2.0
2.5
5.0
6.8
10
Vref (V)
Figure 5.4 Vref Undervoltage Lockout and Overvoltage Protection
UVL Voltage VH VL Vref (V typ) 2.0 V 1.7 V VIN (V typ) 3.6 V 3.3 V Description VIN increasing: UVL releases; PWM output starts VIN decreasing: undervoltage lockout; PWM output stops
Rev.2.0, Sep.18.2003, page 14 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 6. Usage of ON/OFF Pin OFF This pin is used for the following purposes: * To shut down the IC while its input power remains on (power management) * To externally alter the UVL release voltage * With the timer (TM) pin, to operate in intermittent mode during overcurrent (see next section) 6.1 Shutdown by ON/OFF Pin Control OFF The IC can be shut down safely by bringing the voltage at the ON/OFF pin below about 0.7 V (the internal VBE value). This feature can be used in power supply systems to save power. When shut down, the HA16114 draws a maximum current (IOFF) of 10 A, while the HA16120 draws a maximum 150 A. The ON/OFF pin sinks 290 A (Typ) at 5 V, so it can be driven by TTL and other logic ICs. If intermittent mode will also be employed, use a logic IC with an open-collector or open-drain output.
IIN RA External logic IC Off On RB TM VIN To other circuitry To latch 10 k Switch CON/OFF
+ -
VIN
Q1
ON/OFF
Vref reference
Vref output
3VBE Q2 GND HA16114, HA16120 Q3 On/off hysteresis circuit
Figure 6.1 Shutdown by ON/OFF Pin Control OFF 6.2 Adjustment of UVL Voltages (when not using intermittent mode) These ICs permit external adjustment of the undervoltage lockout voltages. The adjustment is made by changing the undervoltage lockout thresholds VTH and VTL relative to VIN, using the relationships shown in the accompanying diagrams. When the IC is powered up, transistor Q3 is off, so VON is 2VBE, or about 1.4 V. Connection of resistors RC and RD in the diagram makes undervoltage lockout release at:
VIN = 1.4 V x RC + RD RD
This VIN is the supply voltage at which undervoltage lockout is released. At the release point Vref is still below 2.5 V. To obtain Vref = 2.5 V, VIN must be at least about 4.3 V. Since VON/OFF operates in relation to the base-emitter voltage of internal transistors, VON has a temperature coefficient of approximately -4 mV/C. Keep this in mind when designing the power supply unit. When undervoltage lockout and intermittent mode are both used, the intermittent-mode time constant is shortened, so the constants of external components may have to be altered.
Rev.2.0, Sep.18.2003, page 15 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
IIN TM (open) ON/OFF 10 k RD 3VBE Q2 GND 3 2 Vref 1 0 VOFF 0.7 V 0 1 VON 1.4 V 2 3 VON/OFF 4 5 VIN To latch Q1 To other circuitry
VIN
RC
Vref generation circuit Q3
Vref output
On/off hysteresis circuit
2.5 V VIN 4.5 V
Figure 6.2 Adjustment of UVL Voltages 7. Timing of Intermittent Mode during Overcurrent 7.1 Principle of Operation These ICs provide pulse-by-pulse overcurrent protection by sensing the current during each pulse and shutting off the pulse if overcurrent is detected. In addition, the TM and ON/OFF pins can be used to operate the IC in intermittent mode if the overcurrent state continues. A power supply with sharp settling characteristics can be designed in this way. Intermittent mode operates by making use of the hysteresis of the ON/OFF pin threshold voltages VON and VOFF (VON - VOFF = VBE). The timing can be programmed as explained below. When not using intermittent mode, leave the TM pin open, and pull the ON/OFF pin up to VON or higher. The VBE is base emitter voltage of internal transistors.
VIN 390 k RA TM Current limiter CL
Latch S Q R Vref reference
2.2 k + 2.2 F -
RB
ON/OFF
CON/OFF
Figure 7.1 Connection Diagram (example)
Rev.2.0, Sep.18.2003, page 16 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 7.2 Intermittent Mode Timing Diagram (VON/OFF only)
3VBE*1 c VON/OFF 2VBE VBE 0V IC is on a IC is off b TON
c On Off On
t
2TON TOFF a. Continuous overcurrent is detected b. Intermittent operation starts (IC is off) c. Voltage if overcurrent ends (thick dotted line) Note: 1. VBE is the base-emitter voltage of internal transistors, and is approximately 0.7 V. (See the figure 6.1.) For details, see the overall waveform timing diagram.
Figure 7.2 Intermittent Mode Timing Diagram (VON/OFF only) 7.3 Calculation of Intermittent Mode Timing Intermittent mode timing is calculated as follows. (1) TON (time until the IC shuts off when continuous overcurrent occurs)
TON = CON/OFF x RB x ln 2VBE VBE x 1 1 - On duty*
1 1 - On duty* 1 0.69 x CON/OFF x RB x 1 - On duty* = CON/OFF x RB x ln2 x
(2) TOFF (time from when the IC shuts off until it next turns on)
TOFF = CON/OFF x (RA + RB) x ln Where VBE 0.7 V VIN - VBE VIN - 2VBE
The greater the overload, the sooner the pulse-by-pulse current limiter operates, the smaller tON becomes, and from the first equation (1) above, the smaller TON becomes. From the second equation (2), TOFF depends on VIN. Note that with the connections shown in the diagram, when VIN is switched on the IC does not turn on until TOFF has elapsed.
Sawtooth wave PWM output (In case of HA16114) tON Dead-band voltage Point at which the current limiter operates tON x 100 (%) T Where T = t/fOSC On duty =
T Note: On duty is the percent of time the IC output is on during one PWM cycle when the pulse-by-pulse current limiter is operating.
Figure 7.3
Rev.2.0, Sep.18.2003, page 17 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ 7.4 Examples of Intermittent Mode Timing (calculated values)
(1) TON TON = T1 x CON/OFF x RB Here, coefficient T1 = 0.69 x 1 1 - On duty T1 2 Example: If CON/OFF = 2.2 F, RB = 2.2 k, and the on duty of the current limiter is 75%, then TON = 13 ms. 6 8
4
from section 7.3 (1) previously.
0
0
20
40
60
80
100
(PWM) On duty (%)
Figure 7.4 Examples of Intermittent Mode Timing (1)
(2) TOFF TOFF = T2 x CON/OFF x (RA + RB) Here, coefficient T2 = ln VIN - VBE VIN - 2VBE T2 0.05 0.1
from section 7.3 (2) previously.
Example: If CON/OFF = 2.2 F, RB = 2.2 k, RA = 390 k, VIN = 12 V, 0 then TOFF = 55 ms.
0
10
20 VIN (V)
30
40
Figure 7.5 Examples of Intermittent Mode Timing (2)
Rev.2.0, Sep.18.2003, page 18 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Sawtooth wave VCT Dead band VDB Error output VE/O PWM pulse output (In case of HA16120) Power MOS FET drain current (ID) (dotted line shows inductor current) VIN Current limiter pin (CL) VIN - 0.2 V IC Example of step-up circuit VIN CF RF CL OUT RCS Inductor L ID VOUT
F.B. Determined by L and VIN VTH (CL) Determined by RCS and RF
Figure 7.6 8. Setting the Overcurrent Detection Threshold The voltage drop VTH at which overcurrent is detected in these ICs is typically 0.2 V. The bias current is typically 200 A. The power MOS FET peak current value before the current limiter goes into operation is given as follows.
ID = VTH - (RF + RCS) x IBCL RCS
Where, VTH = VIN - VCL = 0.2 V, VCL is a voltage refered on GND. Note that RF and CF form a low-pass filter with a cutoff frequency determined by their RC time constant. This filter prevents incorrect operation due to current spikes when the power MOS FET is switched on or off.
VIN To other circuitry CF 1800 pF IBCL CL 1k 200 A
OUT
RCS 0.05
VIN
RF 240 G S D
+
Detector output (internal) IN(-)
-+
VO
-
Note: This circuit is an example for step-down use.
Figure 8.1 Example for Step-Down Use With the values shown in the diagram, the peak current is:
ID = 0.2 V - (240 + 0.05 ) x 200 A = 3.04 A 0.05
The filter cutoff frequency is calculated as follows:
fC = 1 1 = = 370 kHz 2 CF RF 6.28 x 1800 pF x 240
Rev.2.0, Sep.18.2003, page 19 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Absolute Maximum Ratings
(Ta = 25C)
Rating Item Supply voltage Output current (DC) Output current (peak) Current limiter input voltage Error amplifier input voltage E/O input voltage RT source current TM sink current SYNC voltage SYNC current Power dissipation Operating temperature Junction temperature Storage temperature Symbol VIN IO IO peak VCL VIEA VIE/O IRT ITM VSYNC ISYNC PT Topr TjMax Tstg HA16114P/FP, HA16120FP 40 0.1 1.0 VIN VIN Vref 500 3 Vref 250 680* *
1, 2
HA16114PJ/FPJ, HA16120FPJ 40 0.1 1.0 VIN VIN Vref 500 3 Vref 250 680* *
1, 2
Unit V A A V V V A mA V A mW C C C
-40 to +85 125 -55 to +125
-40 to +85 125 -55 to +125
Notes: 1. This value is for an SOP package (FP) and is based on actual measurements on a 40 x 40 x 1.6 mm glass epoxy circuit board. With a 10% wiring density, this value is permissible up to Ta = 45C and should be derated by 8.3 mW/C at higher temperatures. With a 30% wiring density, this value is permissible up to Ta = 64C and should be derated by 11.1 mW/C at higher temperatures. 2. For the DIP package. (P) This value applies up to Ta = 45C; at temperatures above this, 8.3 mW/C derating should be applied.
Permissible dissipation PT (mW)
800 680 mW 600 447 mW 400 348 mW
10% wiring density 30% wiring density
200
45C
64C
85C
125C
0 -40
-20
0
20
40
60
80
100
120
140
Operating ambient temperature Ta (C)
Rev.2.0, Sep.18.2003, page 20 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics
(Ta = 25C, VIN = 12 V, fOSC = 100 kHz)
Item Voltage reference section Output voltage Line regulation Load regulation Short-circuit output current Vref overvoltage protection threshold Temperature stability of output voltage Vref adjustment voltage Sawtooth oscillator section Maximum frequency Minimum frequency Frequency stability with input voltage Frequency stability with temperature Oscillator frequency Dead-band adjustment section Low level threshold voltage High level threshold voltage Threshold difference Output source current PWM comparator section Low level threshold voltage High level threshold voltage Threshold difference Symbol Vref Line Load IOS Vrovp Vref/Ta VADJ fmax fmin f/f01 f/f02 fOSC VTL VTH VTH Isource VTL VTH VTH Min 2.45 -- -- 10 6.2 -- 1.225 600 -- -- -- 90 0.9 1.5 0.5 170 0.9 1.5 0.5 Typ 2.50 2 30 24 6.8 100 1.25 -- -- 1 5 100 1.0 1.6 0.6 250 1.0 1.6 0.6 Max 2.55 60 60 -- 7.4 -- 1.275 -- 1 3 -- 110 1.1 1.7 0.7 330 1.1 1.7 0.7 Unit V mV mV mA V ppm/C V kHz Hz % % kHz V V V A V V V 4.5 V VIN 40 V (f01 = (fmax + fmin)/2) -20C Ta 85C (f02 = (fmax + fmin)/2) RT = 10 k CT = 1300 pF Output duty cycle: 0% on Output duty cycle: 100% on VTH = VTH - VTL DB pin: 0 V Output duty cycle: 0% on Output duty cycle: 100% on VTH = VTH - VTL Test Conditions IO = 1 mA 4.5 V VIN 40V 0 IO 10 mA Vref = 0 V 1 Notes
Note:
1. Resistors connected to ON/OFF pin: 10 VIN pin 390 k 12 TM pin 2 k 13 ON/OFF pin
Rev.2.0, Sep.18.2003, page 21 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25C, VIN = 12 V, fOSC = 100 kHz)
Item Error amplifier section Input offset voltage Input bias current Output sink current Output source current Common-mode input voltage range Voltage gain Unity gain bandwidth High level output voltage Low level output voltage Overcurrent detection section Threshold voltage CL(-) bias current Turn-off time Symbol VIO IB IOsink IOsource VCM AV BW VOH VOL VTH IBCL(-) tOFF Min -- -- 28 28 1.1 40 -- 3.5 -- VIN-0.22 140 -- -- UVL section Vref high level threshold voltage Vref low level threshold voltage Threshold difference VIN high level threshold voltage VIN low level threshold voltage VTH VTL VTH VINH VINL 1.7 1.4 0.1 3.3 3.0 Typ 2 0.5 40 40 -- 50 4 4.0 0.2 VIN-0.2 200 200 500 2.0 1.7 0.3 3.6 3.3 Max 10 2.0 52 52 3.7 -- -- -- 0.5 VIN-0.18 260 300 600 2.3 2.0 0.5 3.9 3.6 Unit mV A A A V dB MHz V V V A ns ns V V V V V VTH = VTH - VTL CL(-) = VIN 1 2 IO = 10 A IO = 10 A f = 10 kHz VO = 2.5 V VO = 1.0 V Test Conditions Notes
Notes: 1. HA16114 only. 2. HA16120 only.
Rev.2.0, Sep.18.2003, page 22 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Electrical Characteristics (cont.)
(Ta = 25C, VIN = 12 V, fOSC = 100 kHz)
Item Output stage Output low voltage Output high voltage High voltage when off Low voltage when off Rise time Fall time External sync section SYNC source current Sync input frequency range External sync initiation voltage Minimum pulse width of sync input Input sync pulse duty cycle On/off section ON/OFF sink current 1 ON/OFF sink current 2 IC on threshold IC off threshold ON/OFF threshold difference Total device Operating current Quiescent current Symbol VOL VOH1 VOH2 VOL2 tr tf ISYNC fSYNC VSYNC PWmin PW ION/ OFF 1 ION/ OFF 2 VON VOFF VON/OFF IIN IOFF Min -- VIN-2.2 VIN-2.2 -- -- -- 120 fOSC Vref-1.0 300 5 60 220 1.1 0.4 0.5 6.0 0 -- Typ 0.9 VIN-1.6 VIN-1.6 0.9 50 50 180 -- -- -- -- 90 290 1.4 0.7 0.7 8.5 -- 120 Max 1.5 -- -- 1.5 200 200 240 fOSC x 2 Vref-0.5 -- 50 120 380 1.7 1.0 0.9 11.0 10 150 Unit V V V V ns ns A kHz V ns % A A V V V mA A A CL = 1000 pF ON/OFF pin: 0 V ON/OFF pin: 0 V 1 2 ON/OFF pin: 3 V ON/OFF pin: 5 V 3 Test Conditions IOsink = 10 mA IOsource = 10 mA IOsource = 1 mA ON/OFF pin: 0 V IOsink = 1 mA ON/OFF pin: 0 V CL = 1000 pF CL = 1000 pF SYNC pin: 0 V 1 2 Notes
Notes: 1. HA16114 only. 2. HA16120 only. 3. PW = t1 / t2 x 100
External sync pulse t1 t2
Rev.2.0, Sep.18.2003, page 23 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Characteristic Curves
Reference Voltage vs. Supply Voltage 4.0 Ta = 25C Reference Voltage vs. Ambient Temperature 2.54 VIN = 12 V 2.55 max Reference voltage (V) 2.52
Reference voltage (V)
3.0
2.5V
2.0
2.50 SPEC 2.48
1.0
2.45 min 0.0 0 1 2 3 4
4.3V
5
40
2.46 -20
0
20
40
60
80
Supply voltage (V)
Ambient temperature (C)
1.5
High level threshold voltage of sawtooth wave (V)
Low level threshold voltage of sawtooth wave (V)
Low Level Threshold Voltage of Sawtooth Wave vs. Frequency 2.5 Ta = 25C VIN = 12 V 2.0 RT = 10 k
High Level Threshold Voltage of Sawtooth Wave vs. Frequency 2.5 Ta = 25C VIN = 12 V 2.0 RT = 10 k
1.5
1.0
1.0
0.5
0.5
0.0 100
200
300
400
500
600
0.0 100
200
300
400
500
600
Frequency (kHz)
Frequency (kHz)
Rev.2.0, Sep.18.2003, page 24 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Oscillator Frequency Change with Ambient Temperature (1) 10 10 Oscillator Frequency Change with Ambient Temperature (2)
5
SPEC
Oscillator frequency change (%)
Oscillator frequency change (%)
VIN = 12 V fOSC = 100 kHz
VIN = 12 V fOSC = 350 kHz 5
0
0
-5
-5
-10 -20
0
20
40
60
80
-10 -20
0
20
40
60
80
Ambient temperature (C)
Ambient temperature (C)
Error Amplifier Gain, Error Amplifier Phase vs. Error Amplifier Input Frequency 60
AVO 40 20 0 45 90
135 0 1k BW 3k 10 k 30 k 100 k 300 k 1M 3M 180 10 M
Error amplifier input frequency fIN (Hz)
Rev.2.0, Sep.18.2003, page 25 of 37
Error amplifier phase (deg.)
Error amplifier gain AVO (dB)
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Error amplifier voltage gain (dB)
55
Current limiter turn-off time (ns)
Error Amplifier Voltage Gain vs. Ambient Temperature 60 VIN = 12 V f = 10 kHz
Current Limiter Turn-Off Time vs. Current Limiter Threshold Voltage Note 500 * HA16114 Ta = 25C VIN = 12 V CL = 1000 pF
400
50
50 dB typ
300
300 ns max
45
200
40 dB min 40 -20 0 20 40 60 Ambient temperature (C) 80 100 0.1 0.2 0.3 0.4 0.5 CL voltage VIN-VCL (V) Note: Approximatery 300 ns greater than this in the case of the HA16120. Current Limiter Turn-Off Time vs. Ambient Temperature Note * HA16114 300 ns max
0.22
Current limiter threshold voltage (V)
Current Limiter Threshold Voltage vs. Ambient Temperature VIN = 12 V 0.22 max
Current limiter turn-off time (ns)
300
0.21
250
0.20
200 200 ns typ VIN = 12 V 150 VCL = VTH - 0.3 V CL = 1000 pF 100 -20
0.19
0.18 min 0.18 -20 0 20 40 60 Ambient temperature (C) 80 0 20 40 60 80 Ambient temperature (C) Note: Approximatery 300 ns greater than this in the case of the HA16120.
Rev.2.0, Sep.18.2003, page 26 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Reference Voltage vs. IC On/Off Voltages 5.0 Ta = 25C VIN = 12 V 4.0
Reference voltage (V) IC on/off voltage (V)
IC On/Off Voltages vs. Ambient Temperature 2.0 VIN = 12 V fOSC = 100 kHz 1.5 SPEC IC on voltage 1.0
3.0
IC off voltage
IC on voltage
SPEC IC off voltage
2.0
SPEC
SPEC
0.5
1.0
0.0
0
0.5
1.0
1.5
2.0
2.5
0.0 -20
0
20
40
60
80
IC on/off voltage (V)
Ambient temperature (C)
Peak output current (mA)
Peak Output Current vs. Load Capacitance 600 Ta = 25C VIN = 12 V 500 f OSC = 100 kHz 400 300 200 100 0
Operating current (mA)
Operating Current vs. Supply Voltage 20 Ta = 25C fOSC = 100 kHz On duty = 50% CL = 1000 pF SPEC
15
10
5
0
1000
2000
3000
4000
5000
0
0
10
20
30
40
Load capacitance (pF)
Supply voltage (V)
Rev.2.0, Sep.18.2003, page 27 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Operating Current vs. Output Duty Cycle 20 Ta = 25C VIN = 12 V fOSC = 100 kHz CL = 1000 pF SPEC 10
Operating current (mA)
15
5
0
0
20
40
60
80
100
Output duty cycle (%)
PWM Comparator Input vs. Output Duty Cycle (1) 100 * HA16114 80
ON duty (%)
PWM Comparator Input vs. Output Duty Cycle (2) 100 * HA16120 80
ON duty (%)
60
60 fOSC 600 kHz 40 300 kHz 50 kHz
40
fOSC 600 kHz
50 kHz 20
20 300 kHz 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0 0.6
0.8
1.0
1.2
1.4
1.6
1.8
VDB or VE/O (V) Note: The on-duty of the HA16114 is the proportion of one cycle during which output is low.
VDB or VE/O (V) Note: The on-duty of the HA16120 is the proportion of one cycle during which output is high.
Rev.2.0, Sep.18.2003, page 28 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Output pin (Output Resistor) Characteristics 12 * HA16114 Output high voltage 11 when on
Output voltage VO (VDC)
VGS (P-channel Power MOS FET)
10 9 * HA16120 Output low voltage when on Output low voltage when off 0 2 4 6 8 10 Output high voltage when off
3 2 1 0
VGS (N-channel Power MOS FET)
Io sink or Io source (mA)
Rev.2.0, Sep.18.2003, page 29 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Output Waveforms: Rise of Output Voltage VOUT 15 10 VOUT (V) 5 0 400 200 IO (mA) 10 k 0 -200 -400
200 ns/div
Vref DB
CL(-) VIN OUT CL 1000 pF IO
IN(+) RT
CT 1300 pF
Test Circuit
Output Waveforms: Fall of Output Voltage VOUT 15 10 VOUT (V) 5 0 400 200 IO (mA) 10 k 0 -200 -400
200 ns/div
Vref DB
CL(-) VIN OUT CL 1000 pF IO
IN(+) RT
CT 1300 pF
Test Circuit
Rev.2.0, Sep.18.2003, page 30 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Oscillator Frequency vs. Timing Capacitance
1000
100
RT = 3k RT = 10k RT = 30k
Oscillator frequency fOSC (kHz)
10
RT = 100k RT = 300k RT = 1M
1
0.1 1 10
102
103
104
105
106
Timing capacitance CT (pF)
Rev.2.0, Sep.18.2003, page 31 of 37
* 12 VDC to 5 VDC Step-Down Converter Using HA16114FP 390 k Timing circuit for intermittent mode during overcurrent 2k
+
50m 220
-
Overcurrent sense resistor Low on-resistance P-channel power MOSFET Example: 2SJ214, 2SJ296 GDS High-saturation-current choke coil Example: Toko 8R-HB Series 2
Dead-band and soft-start circuit 2 1800p 5D 5.6 (gate protection resistor) 47H
16
Vref HA16114FP GND ADJ DB ON/OFF TM CL(-) VIN OUT
1
Application Examples (1)
- +
Rev.2.0, Sep.18.2003, page 32 of 37
4.7 15 k 0.1
15 14 13 12 11 10 9
+ 10 k
+
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
+
-
12 V DC input - SBD
SYNC
RT CT IN(-) E/O IN(+) P.GND
+ -
5B 470 35 V (noiseabsorbing capacitor)
1 2 3 4 5 6 7 8
5C Ground strip 470p 10k 560p 130k Feedback Small-signal ground
0.22 (noiseabsorbing capacitor)
3 HRP24
Low-ESR capacitor 560 12V 4
5 V DC steppeddown output -
Power ground 5k
5A 5k
5A
Specific tips for high efficiency (see the numbers in the diagram)
Units: C : F R: 5 Noise countermeasures: 5A Separate the power ground from the small-signal ground, and connect both at one point. 5B Add noise-absorbing capacitors. 5C Ground the bottom of the package with a ground strip. 5D Make the output-to-gate wiring as short as possible.
1 2 3 4
Use a switching element (power MOS FET) with low on-resistance. Use an inductor with low DC resistance. Use a Schottky barrier diode (SBD) with low VF. Use a low-ESR capacitor designed for switching power supplies.
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (2)
* External Synchronization with Primary-Control AC/DC Converter (1) Combination with a flyback AC/DC converter (simplified schematic) HRA83 Commercial AC
+ -
Transformer 1S2076A 1S2076A
+
HRP24 + SBD
+ -
D R1 R2
Main DC output -
Error amp.
- +
VIN OUT CL(CS) 2 VIN 10 HA16114, HA16120 CL 11 GND OUT P.GND 1 9 8
SYNC
Primary AC/DC converter IC (HA16107, HA17384, etc.)
To A of SBD 2SJ296 + Step-down output (HA16114) K A SBD HRP24
+ -
Sub DC output -
This is one example of a circuit that uses the features of the HA16114/120 by operating in synchronization with a flyback AC/DC converter. Note the following design points concerning the circuit from the secondary side of the transformer to the SYNC pin of the HA16114/120. * Diode D prevents reverse current. Always insert a diode here. Use a general-purpose switching diode. * Resistors R1 and R2 form a voltage divider to ensure that the input voltage swing at the SYNC pin does not exceed Vref (2.5 V). To maintain operating speed, R1 + R2 should not exceed 10 k.
Rev.2.0, Sep.18.2003, page 33 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (3)
* External Synchronization with Primary-Control AC/DC Converter (cont.) (2) Combination with a forward AC/DC converter (simplified schematic)
DFG1C8 D Input HRW26F HA17431 and optocoupler +
C A B
SBD module
Feedback section
Main DC output -
HA16107, HA16666 etc.
FB 2SC458 R3 390 2 Q R2 510 VIN 10 9 Other parts as on previous page
Switching transformer Coil Coil Coil Coil A B C D Primary, for main Secondary, for output Tertiary, for IC For reset
R1
6.2k
SYNC VIN HA16114, HA16120 OUT ZD GND 1
This circuit illustrates the combination of the HA16114/120 with a forward AC/DC converter. The HA16114/120 synchronizes with the falling edge of the external sync signal, so with a forward transformer, the sync pulses must be inverted. In the diagram, this is done by an external circuit consisting of the following components: * Q: Transistor for inverting the pulses. Use a small-signal transistor. * R1 and R2: These resistors form a voltage divider for driving the base of transistor Q. R2 also provides a path for base discharge, so that the transistor can turn off quickly. * R3: Load resistor for transistor Q. Zener diode for protecting the SYNC pin. * ZD:
Rev.2.0, Sep.18.2003, page 34 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Overall Waveform Timing Diagram (for Application Example (1))
12 V VIN 0V 2.1 V 1.4 V VTM, VON/OFF 1.4 V 0.7 V
VTM, VON/OFF 0.0 V
On (V) 3.0 VE/O Off 2.0 VE/O, VCT, VDB 1.0 VDB 0.0 VCL 12 V 11.8 V 0V Pulse-by-pulse current limiting VOUT*1 12 V PWM pulse 0 V DC/DC output (example for positive voltage) VCT sawtooth wave Off On On On Off Off Off On
Soft start IC operation status Power-up IC on
Steady state
Overcurrent detected; intermittent operation
Overcurrent Quick subsides; shutdown steady-state operation Power supply off, IC off
Note: 1. This PWM pulse is on the step-down/inverting control channel (HA16114). The booster control channel (HA16120) output consists of alternating L and H of the IC on cycle.
Rev.2.0, Sep.18.2003, page 35 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Application Examples (4) (Some Pointers on Use)
1. Inductor, Power MOS FET, and Diode Connections
1. Step-up topology VIN CF VIN CL VO OUT GND FB GND FB RF RCS Applicable only to HA16120 2. Step-down topology V IN CF VIN CL OUT VO RF RCS Applicable only to HA16114
3. Inverting topology CF VIN CL OUT VO RF
4. Step-down/step-up (buck-boost) topology CF VIN CL OUT RF
RCS
Applicable only to HA16114
RCS
Applicable only to HA16114
GND FB Vref
GND FB
2. Turning Output On and Off while the IC is On
To turn only one channel off, ground the DB pin or the E/O pin. In the case of E/O, however, there will be no soft start when the output is turned back on. DB
E/O OFF
Rev.2.0, Sep.18.2003, page 36 of 37
HA16114P/PJ/FP/FPJ, HA16120FP/FPJ
Package Dimensions
As of January, 2003
Unit: mm
9
7.40 Max 6.30
19.20 20.00 Max 16
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
Package Code JEDEC JEITA Mass (reference value)
+ 0.13
DP-16 Conforms Conforms 1.07 g
As of January, 2003
10.06 10.5 Max 16 9
Unit: mm
1
*0.22 0.05 0.20 0.04
8
0.80 Max
5.5
0.20 7.80 + 0.30 -
2.20 Max
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.42 0.08 0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DA -- Conforms 0.24 g
*Dimension including the plating thickness Base material dimension
Rev.2.0, Sep.18.2003, page 37 of 37
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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